DDR4のボード設計については、アプリケーションノートが用意されています。（AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces - Application Note）こちらの資料をご参考ください。
以下は、こちらの資料に記載されている配線長の制約です。

 

<No26>
Across all DDR4 data lanes:
●Ensure that all the data lanes are matched within 2.0 inches.

<No28>
Ensure that each data lane properly is trace-matched to within 20 mils of its respective differential data strobe.
●Ensure the tace matching for parts with operational data rates of higher than 1600MT/s is within +/-5 mils.

<No30>
MDQS/MDQS_B considerations:
●Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MDQS/MDQS_B pair to be within +/-5 mils.
...
●Diff gap = 4-5 mils(as DQS signals are not true differential, also known as "pseudo differential")
●Diff gap = 5-8 mils for parts with operational speeds of higher than 1600MT/s.

<No.32>
ensure clocks are routed as a differential pair, with the following recommendations:
●P-to-N tuning = +/-5 mils
...
NOTE: The clock signal trace length from the memory controller to any given DDR4 chip should be longer than its corresponding strobe trace length.

<No36>
Ensure all clock pairs are properly trace matched to address/command/control signals within 25 mils.

<No39>
Check the skew between the clock and corresponding strobe for each byte lane. The clock and strobe trace length should be measured from the memory controller pin to the DDR4 DRAM chip pin. After obtaining the MCK to DQS skew for each byte lane, ensure max skew is less than 10 inches.