(from Revision * (January 2021) to Revision A (July 2021))
・Added Velocity Compensation section
・Updated DDR4 Interface Schematics section
・Updated 32-Bit, Single-Rank DDR4 Implementation With ECC Using x16 SDRAMs image
・Updated 32-Bit, Single-Rank DDR4 Implementation With ECC Using x8 SDRAMs image
・Updated VREF Routing section
・Updated Data Group Topologies and Routing Guidance section
・Updated CK and ADDR_CTRL Routing Limits section
・Updated CK and ADDR_CTRL Routing Specifications table
・Updated Data Group Routing Limits section
・Updated Data Group Routing Specifications table.