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2.8 DDR

AM64x/AM243x DDR Board Design and Layout Guidelines

（文書番号：spracu1) [英語版]


AM64x / AM243xDDRボードの設計とレイアウトのガイドラインにある
すべての推奨事項が網羅されていることを確認してください。
 

Table of Contents                                                                                      

1 Overview
 

1.1 Board Designs Supported
1.2 General Board Layout Guidelines
1.3 PCB Stack-Up
1.4 Bypass Capacitors
1.5 Velocity Compensation
 

2 DDR4 Board Design and Layout Guidance
 

2.1 DDR4 Introduction
2.2 DDR4 Device Implementations Supported
2.3 DDR4 Interface Schematics
2.4 Compatible JEDEC DDR4 Devices
2.5 Placement
2.6 DDR4 Keepout Region
2.7 VPP
2.8 Net Classes
2.9 DDR4 Signal Termination
2.10 VREF Routing
2.11 VTT
2.12 POD Interconnect
2.13 CK and ADDR_CTRL Topologies and Routing Guidance
2.14 Data Group Topologies and Routing Guidance
2.15 CK and ADDR_CTRL Routing Specification
2.16 Data Group Routing Specification
2.17 Bit Swapping
 
3 LPDDR4 Board Design and Layout Guidance

3.1 LPDDR4 Introduction
3.2 LPDDR4 Device Implementations Supported
3.3 LPDDR4 Interface Schematics
3.4 Compatible JEDEC LPDDR4 Devices
3.5 Placement
3.6 LPDDR4 Keepout Region
3.7 Net Classes
3.8 LPDDR4 Signal Termination
3.9 LPDDR4 VREF Routing
3.10 LPDDR4 VTT
3.11 CK and ADDR_CTRL Topologies
3.12 Data Group Topologies
3.13 CK and ADDR_CTRL Routing Specification
3.14 Data Group Routing Specification
3.15 Channel, Byte, and Bit Swapping

 

 

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